A charge storage layer of a flash memory is used to store data by trapping electrons. The charge storage layer includes a silicon-oxide-nitride-oxide silicon (SONOS) type structure which stores the electrons in a trap layer made of an oxide-nitride-oxide (ONO) film. U.S. Pat. No. 6,011,725 is a related art which discloses a flash memory with the SONOS type structure, where each transistor of the flash memory can store two data bits by forming two charge storage regions between each source and drain which is interchangeable.
FIG. 1 is a top view of the flash memory as described in the related art. In FIG. 1, bit lines 60 are buried in a semiconductor substrate 10. Wordlines 62 are provided on the semiconductor substrate 10 via an ONO film (not shown). The wordlines 62 intersect the bit lines 60. The portion of the semiconductor substrate 10 below the wordlines 62 and between the bit lines 60 serves as a channel. Each of the bit lines 60 can serve as a source or a drain of the flash memory, whereas each of the wordlines 62 serves as a gate. A high electric field is applied between the bit line 60 (BL1), which functions as the source, and the bit line 60 (BL2), which functions as the drain, so that electrons are stored in the charge storage region C01 in the ONO film. Meanwhile, the electrons may be stored in the charge storage region C02 by switching the source and drain of the flash memory. The symmetrical operation of the source and the drain makes it possible to form two charge storage regions (e.g., C01 and C02) in the ONO film between the source and the drain. Thus, two bits can be stored in a single transistor of the flash memory.
However, as the width of the wordline 62 is shortened to reduce the size of the flash memory, the widths of the charge storage regions C01 and C02 in the ONO film also need to be reduced. The reduction of the widths may decrease the charge quantity of the electrons stored in the charge storage regions C01 and C02. For example, if the width of either C01 or C02 becomes 0.2 um or less, a charge loss in each region due to the reduction may become significant. It is therefore a reason which prevents chip makers from further reducing the size of the flash memory.